1. Field of the Invention
The present invention generally relates to a dynamic memory structure. Specific words, the present invention relates to a dynamic memory structure with a split gate, a shared capacitor unit and a shared source terminal.
2. Description of the Prior Art
A dynamic random access memory (DRAM) structural unit is a memory structural unit which is formed by a metal oxide semiconductor (MOS) connected to a capacitor in series. A metal oxide semiconductor transistor includes a gate as well as at least two sets of doped regions, respectively serving as a drain or a source. A metal oxide semiconductor transistor is controlled to switch on or off by the word line which is electrically connected to the gate, and by the drain which is electrically connected to a bit line to form a current path to achieve the purposes of data storage or input through a storage node which is electrically connected to a capacitor via the source.
In the current dynamic random access memory processes, the capacitors are usually designed to be either a stacked capacitor which is stacked on the substrate surface, or a deep trench capacitor which is buried in the substrate. No matter what kind of the dynamic random access memory is involved, there is only one gate to control the switch on or off of the gate channel which is buried in the substrate, and in addition a capacitor which is electrically connected to the source is constructed to achieve the purpose of data storage or output.
With the trends toward miniaturization of electronic products, the design of the dynamic random access memory element must meet the requirements of high-integration and high density. And scale-down the size of the design of the transistor components is effective to enhance the integration of the integrated circuits such as the dynamic random access memory. When the scale-down of the size of the transistor elements hits the limits, a three-dimensional (3D) transistor, such as fin-shaped structure, is considered to be another way out.
In addition, in order to promote the dynamic random access memory devices to have good performance, the length of the channel region is usually required to be at least twice greater than the width of the channel region in three-dimensional transistors, but this is not advantageous to scale down the size of the design of the transistor elements.
In view of this, a new dynamic random access memory structure is still needed to have a smaller memory cell size, without limiting the ratio of the length to the width of the channel region, to further reduce the costs and to be more popular.